nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20nm technology. In SRAM 

and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved 

data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error 

correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that 

m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results 

showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.