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publication 2016-12-25
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[2] A. Ahmed, K.-B. Park, and Sanghyeon Baeg, "Exploitation of Performance Parameters Trade-Off in Emulated TCAM," IEEE Electronics letters, Submitted

[1] A. Ahmed, K.-B. Park, and Sanghyeon Baeg, "Logic Synthesis-Based Approach to Emulate Ternary Content Addressable Memory using SRAM," IEEE Electronics letters, Submitted


International Journals

[37] C.-S. Lim, K.-B. Park, and Sanghyeon Baeg, "Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Proton in 3x-nm SDRAM," IEEE Trans. Nucl. Sci., Accepted for publication

[36] H.-S. Lee, Sanghyeon Baeg, N. Hua, and S.-J. Wen, "Temporal and Frequency Characteristic Analysis of Margin-related Failures Caused by an Intermittent Nano-scale Fracture of the Solder Ball in a BGA Package Devices," Microelectron. Reliab., Accepted for publication

[35] S. A. Khan, C.-S. Lim, G.-Y. Bak, Sanghyeon Baeg, and S.-Y. Lee, "An Alternative Approach to Measure Alpha-Particle-Induced SEU Cross-Section for Flip-Chip Packaged SRAM Devices: High Energy Alpha Backside Irradiation," Microelectron. Reliab., Accepted for publication

[34] A. Ahmed, K.-B. Park, and Sanghyeon Baeg, "Resource-Efficient SRAM-based Ternary Content Addressable Memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. no. pp. Dec. 2016

[33] K.-B. Park, D.-H. Yun, and Sanghyeon Baeg, "Statistical Distribution of Row-Hammering Induced Failures in DDR3 Components," Microelectron. Reliab., vol. 67, pp. 143-149, Dec. 2016

[32] H.-B. Wang, L. Chen, R. Liu, Y.-Q. Li, J. S. Kauppila, B. L. Bhuva, K. Lilja, S.-J. Wen, R. Wong, R. Fung, and Sanghyeon Baeg, "An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology," IEEE Trans. Nucl. Sci., vol. 63, no. 6, pp. 3003-3009, Dec. 2016

[31] Y. Li, H.-B. Wang, R. Liu, L. Chen, I. Nofal, Q. Chen, A. He, G. Guo, Sanghyeon Baeg, S.-J. Wen, R. Wong, Q. Wu, and M. Chen, "A 65 nm Temporally Hardened Flip-Flop Circuit," IEEE Trans. Nucl. Sci., vol. 63, no. 6, pp. 2934-2940, Dec. 2016

[30] H.-B. Wang, J. S. Kauppila, K. Lilja, M. Bounasser, L. Chen, M. Newton, Y.-Q. Li, R. Liu, B. Bhuva, S.-J. Wen, R. Wong, R. Fung, Sanghyeon Baeg, and L. W. Massengill, "Evaluation of SEU Performance of 28-nm FDSOI Flip-flop Designs," IEEE Trans. Nucl. Sci., vol., no., pp., Nov. 2016

[29] S. A. Khan, S.-J. Wen, and Sanghyeon Baeg, "Assessing Alpha-particle-induced SEU Sensitivity Using High Energy Irradiation," IEICE Electronics Express, vol. 13, no. 17, pp. 1-6, Sep. 2016

[28] K.-B. Bark, C.-S. Lim, D.-H. Yun, and Sanghyeon Baeg, "Experiment and Root Cause Analysis for Active-Precharge Hammering Fault in DDR3 SDRAM under 3x nm Technology," Microelectron. Reliab., vol. 57, pp. 39-46, Feb. 2016

[27] H.-B. Wang, N. Mahatme, L. Chen, M. Newton, Y.-Q. Li, R. Liu, M. Chen, B. L. Bhuva, K. Lilja, S.-J. Wen, R. Wong, R. Fung, and Sanghyeon Baeg, "Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology," IEEE Trans. Nucl. Sci., vol. 63, no. 1, pp. 385-391, Feb. 2016

[26] Q. Wu, Y.-Q. Li, L. Chen, A.-L. He, G. Guo, Sanghyeon Baeg, H.-B. Wang, S.-J Wen, R. Wong, S. Allman, and R. Fung, "Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs," IEEE Trans. Nucl. Sci., vol. 62, no. 4, pp. 1898-1904, Apr. 2015

[25] H.-B. Wang, B. L. Bhuva, S.-J. Wen, R. Wong, Sanghyeon Baeg, N. Mahatme, Y. Li, R. Liu, and L. Chen, "An SEU-Tolerant DICE Latch Design with Feedback Transistors," IEEE Trans. Nucl. Sci., vol. 62, no. 2, pp. 548-554, Apr. 2015

[24] C.-S. Lim, H.-S. Jeong, G.-Y. Bak, Sanghyeon Baeg, S.-J. Wen, and R. Wong, "Stuck Bits Study in DDR3 SDRAMs using 45-MeV Proton Beam," IEEE Trans. Nucl. Sci., vol. 62, no. 2, pp. 520-526, Apr. 2015

[23] H.-B. Wang, M.-L. Li, L. Chen, Sanghyeon Baeg, S.-J. Wen, R. Wong, R. Fung, and J. Bi, "Single Event Resilient Dynamic Logic Designs," Journal of Electronic Testing: Theory and Applications, vol. 30, no. 6, pp. 751-761, Dec. 2014

[22] S.-H. Jeon, S.-Y. Lee, Sanghyeon Baeg, I.-G. Kim, and G. Kim, "Novel Error Detection Scheme with the Harmonious usage of Parity codes, Well-taps, and Interleaving Distance," IEEE Trans. Nucl. Sci., vol. 61, no. 5, pp. 2711-2717, Sep. 2014

[21] J. A. Maestro, P. Reviriego, Sanghyeon Baeg, S.-J. Wen, and R. Wong, "Soft Error Tolerant Content Addressable Memories (CAM) Using Error Detection Codes and Duplication," Journal of Microprocessors and Microsystems, vol. 37, no. 8, pp. 1103-1107, Nov. 2013

[20] S. M. Abbas, S.-Y. Lee, Sanghyeon Baeg, and S. Park, "An Efficient Multiple Cell Upstes Tolerant Content-Addressable Memory, " IEEE Trans. Computers, vol. 63, no. 8, pp. 2094-2098, Apr. 2013

[19] S.-Y. Lee, S.-H. Jeon, Sanghyeon Baeg, and D.-H. Lee, "Memory Reliability Analysis for Multiple Block Effect of Soft Errors," IEEE Trans. Nucl. Sci., vol. 60, no. 2, pp. 1384-1389, Apr. 2013

[18] Z. Ullah, and Sanghyeon Baeg, "Vertically Partitioned SRAM-based Ternary Content Addressable Memory," International Journal of Engineering and Technology, vol. 4, no. 6, pp. 760-764, Dec. 2012

[17] Z. Ullah, I.-G. Kim, and Sanghyeon Baeg, "Hybrid Partitioned SRAM-based Ternary Content Addressable Memory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2969-2979, Dec. 2012

[16] J.-S. Bae, Sanghyeon Baeg, and S.-J. Park, "Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress," IEEE Trans. on Instrum. Meas., vol. 61, no. 12, pp. 3259-3272, Oct. 2012

[15] Sanghyeon Baeg, S.-Y. Lee, G.-Y. Bak, H.-S. Jeong, and S.-H. Jeon, "Comparative Study of MC-50 and ANITA Neutron Beams by Using 55 nm SRAM, "Journal of the Korean Physical Society, vol. 61, no. 5, pp. 749-753, Sep. 2012

[14] S.-Y. Lee, Sanghyeon Baeg, and P. Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors," IEEE Trans. Nucl. Sci., vol. 58, no. 5, pp. 2483-2492, Oct. 2011

[13] J. A. Maestro, P. Reviriego, Sanghyeon Baeg, S.-J. Wen, and R. Wong, "Mitigating the effects of large Multiple Cell Upsets (MCUs) in Memories," ACM Trans. on Design Auto. of Elec. Syst., vol. 16, no. 4, pp. 45:1-45:10, Oct. 2011

[12] P. Reviriego, J. A. Maestro, Sanghyeon Baeg, S.-J Wen, and R. Wong, "Protection of Memories Suffering MCUs through the Selection of the Optimal Interleaving Distance," IEEE Trans. Nucl. Sci., vol. 57, no. 4, pp. 2124-2128, Aug. 2010

[11] P. Reviriego, J. A. Maestro, and Sanghyeon Baeg, "Optimizing Scrubbing Sequences for Advanced Computer Memories," IEEE Trans. Device Mater. Rel., vol. 10, no. 2, pp. 192-200, Jun. 2010

[10] Sanghyeon Baeg, S.-J. Wen, and R. Wong, "Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 814-822, Apr. 2010

[9] Sanghyeon Baeg, S.-J. Wen, and R. Wong, "SRAM Interleaving Distance Selection with a Soft Error Failure Model," IEEE Trans. Nucl. Sci., vol. 56, no. 4, pp. 2111-2118, Aug. 2009

[8] Sanghyeon Baeg, "Null Detector Circuit Design Scheme for Detecting Defective AC Coupled Capacitors in Differential Signaling," IEEE Trans. Instrum. Meas., Vol. 58, No. 8, pp.2544-2556, Aug. 2009

[7] Sanghyeon Baeg, "A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins," IEEE Trans. Instrum. Meas., vol. 58, no. 10, pp. 3450-3456, Oct. 2009

[6] Sanghyeon Baeg, "Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line," IEEE Trans. Circuits Syst. I, Reg. Papers, Vol.55, No.6, pp. 1485-1494, Jul. 2008

[5] Sanghyeon Baeg, "Low Power Configuration Strategy of TCAM Lookup Table," IEICE Trans. on Communications, vol. 91-B, no.3, pp. 915-917, Mar. 2008

[4] Sanghyeon Baeg, "Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks," IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 26, no. 12, pp. 2215-2221, Dec. 2007

[3] P. Min, H. Yi, J. Song, Sanghyeon Baeg, and S. Park, "Efficient Interconnect Test Patterns for Crosstalk and Static Faults," IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 25, no. 11, pp. 2605-2608, Nov. 2006

[2] Sanghyeon Baeg, and S. Chung, "Analytical Test Buffer Design For Differential Signaling I/O Buffers By Error Syndrome Analysis," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 3, pp. 370-383, Mar. 2005

[1] Sanghyeon Baeg, and W. A. Rogers, "A Cost-Effective Design for Testability: Clock Line Control and Test Generation Using Selective Clocking," IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 18, no. 6, pp. 850-861, June 1999


International Conferences

[32] M.-S. Park, S.-H. Jeon, G.-Y. Bak, C.-S. Lim, Sanghyeon Baeg, S.-J. Wen, R. Wong, N. Yu, "Soft Error Study with DDR4 SDRAMs Using 480 MeV Proton Beam," IEEE International Reliability Physics Symposium (IRPS), Apr. 2017

[31] G. Ramasamy, S.-J. Jeong, Sanghyeon Baeg, N. Hua, Y. Lee, "HBM Memory Fault Grading and Results," IEEE International Test Conference (ITC), Nov. 2016

[30] G.-Y. Bak, S.-Y. Lee, H.-S. Lee, K.-B. Park, Sanghyeon Baeg, S.-J. Wen, R. Wong, and C. Slayman, "Logic Error Study with 800-MHz DDR3 SDRAMs in 3x nm Using Proton and Neutron Beams," IEEE International Reliability Physics Symposium (IRPS), Apr. 2015

[29] K.-B. Park, Sanghyeon Baeg, S.-J. Wen, and R. Wong, "Active-Precharge Hammering on a Row Induced Failure in DDR3 SDRAMs under 3x nm Technology," IEEE International Reliability Workshop (IIRW), Oct. 2014

[28] K. Lilja, H.-B. Wang, M. Bounasser, N. Mahatme, S.-J. Wen, R. Wong, R. Fung, Sanghyeon Baeg, B. Bhuva, and L. Chen, "Voltage Dependence of Single Event Error Rates for Flip-Flops in Advanced Technologies - from Nominal to Near Threshold," Single Event Effect (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, May. 2014

[27] H.-B. Wang, Li Chen, K. Lilja, M. Bounasser, N. Mahatme, B. Bhuva, S.-J. Wen, R. Wong, R. Fung, Sanghyeon Baeg, "Impact of Well Ties on Single Event Transient Width," Single Event Effect (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, May. 2014

[26] Sanghyeon Baeg, "MCU Effects on SER Modeling with Memory Architecture Parameters," International school on the Effects on Radiation on Embedded Systems for Space Applications (SERESSA), Dec. 2012

[25] X. Gu, and Sanghyeon Baeg, "Why Memory Test Is Still a Challenge?," SEMICON China 2012, Mar. 2012

[24] Sanghyeon Baeg, S.-Y. Lee, K. Y. Park, S.-J. Wen, and R. Wong, "High-Energy Alpha Particle SEU Measurements for Flip Chip Devices," IEEE Santa Clara Valley CPMT Society Chapter Workshop, Oct. 2012

[23] Sanghyeon Baeg, J.-S. Bae, S.-Y. Lee, C.-S. Lim, S.-H. Jeon, and H.-W. Nam, "Soft Error Issues with Scaling Technologies," The 21st Asian Test Symposium (ATS'12), Nov. 19-22, 2012

[22] J. A. Maestro, A. Sánchez-Macián, P. Reviriego, Sanghyeon Baeg, "Optimizing the Protection of Narrow Values in Memories Protected with Hamming Codes," Proc. of the conference on Radiation and its Effects on Components and Systems (RADECS), Biarritz (France), Sep. 2012

[21] Sanghyeon Baeg, P. Chia, S.-J. Wen, and R. Wong, "DRAM Failure Cases Under Hot-Carrier Injection," IEEE International Symp. on Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 1-3, July 2011

[20] P. Reviriego, J. A. Maestro, and Sanghyeon Baeg, "Designing Ad-Hoc Scrubbing Sequences to Improve Memory Reliability against Soft Errors," Design Automation Conference (DAC), pp. 700-705, June 2011

[19] Sanghyeon Baeg, H.-W. Nam, S.-J. Wen and R. Wong, "AC-DC Factor Sensitivity for DRAM Components Lifetime under Hot-Carrier Injection," IEEE International Reliability Physics Symposium (IRPS), pp. 2D.1.1-1.4, April 2011

[18] S. M. Abbas, Sanghyeon Baeg, S.-J. Park, "Multiple Cell Upsets Tolerant Content-Addressable Memory," IEEE International Reliability Physics Symposium (IRPS), pp. SE.1.1-1.5, April 2011

[17] C.-M. Jung, Sanghyeon Baeg, S.-J. Wen, and R. Wong, "Design Method of NOR-Type Comparison Circuit in CAM with Ground Bounce Noise Considerations," International Symposium on Quality Electronic Design (ISQED), pp. 1-8, March 2011

[16] C.-F. Chia, S.-J. Wen, and Sanghyeon Baeg, "New DRAM HCI Qualification Method Emphasizing on Repeated Memory Access," IEEE International Integrated Reliability Workshop (IIRW), pp. 142-144, Oct. 2010

[15] Z. Ullah and Sanghyeon Baeg, "Vertically Partitioned SRAM-based Ternary Content Addressable Memory," IEEE International Conference on Intelligence and Information Technology (ICIIT), Oct. 2010

[14] J.-S. Bae, Sanghyeon Baeg, S.-J. Wen, and R. Wong, "SRAM Cell Reliability Degradations due to Cell Crosstalk," IEEE International Integrated Reliability Workshop (IIRW), pp. 129-132, Oct. 2010

[13] S.-Y. Lee, Sanghyeon Baeg, and P. Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors," IEEE International Integrated Reliability Workshop (IIRW), pp. 114-117, Oct. 2010

[12] P. Reviriego, J. A. Maestro, Sanghyeon Baeg, S.-J. Wen and R. Wong, "Selection of the Optimal Interleaving Distance for Memories Suffering MCUs," Proc. of the conference on Radiation and its Effects on Components and Systems (RADECS),  Sep. 2009

[11] Sanghyeon Baeg, P. Reviriego, J. A. Maestro, S.-J. Wen, and R. Wong, "Analysis of a Multiple Cell Upset Failure Model for Memories," SELSE 5 Workshop - Silicon Errors in Logic - System Effects, March 2009

[10] H.-D. Shin, S.-W. Ahn, T.-H. Song, and Sanghyeon Baeg, "Analysis of Low Power Sensor Node Using Data Compression," 8th IFAC International Conference on Fieldbuses and Networks in industrial and embedded systems (FeT), pp. 34-39, May 2009

[9] Sanghyeon Baeg, S.-J. Wen, and R. Wong, "SRAM Interleaving Distance Selection with a Soft Error Failure Model, "Proc. of the conference on Radiation and its Effects on Components and Systems (RADECS),  Sep. 2008

[8] L. Boluna, K. Qiu, E. Kabir, S. Mutsuddy, D. Ho, and Sanghyeon Baeg, "Advances in 7.5Gb/s SerDes Modeling using IBISv4.2(VHDL-AMS and Verilog-AMS)," IBIS Summit Meeting, Santa Clara, CA., U.S.A, Feb 7, 2008

[7] H. Jun, S. Chung, and Sanghyeon Baeg, "Removing JTAG Bottleneck in System Interconnect Test," Proc. Int’l Test Conf. (ITC), pp. 173-180, Oct. 2004

[6] S. Chung and Sanghyeon Baeg, "AC-JTAG: Empowering JTAG beyond Testing DC Nets," Proc. Int’l Test Conf. (ITC), pp. 30-37, 2001

[5] Sanghyeon Baeg, H. R. Kim, C. H. Cho, and H. C. Kim, "Embedded Memory BIST of Serial Test Vector Generation, Serial Output Comparison," Second International Test Synthesis Workshop, May 1995

[4] Sanghyeon Baeg and W. A. Rogers, "Hybrid Design For Testability Combining Scan and Clock Line Control and Method For Test Generation," Proc. Int’l Test Conf. (ITC), pp. 340-349, Oct. 1994

[3] Sanghyeon Baeg and W. A. Rogers, "A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits," IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 354-358, Oct. 1994

[2] Sanghyeon Baeg and W. A. Rogers, "Enhancing Temporal Testability and Its Effects on Design and Test Generation," Proc. in International Workshop on The Economics of Design, Test and Manufacturing, May 1994

[1] Sanghyeon Baeg and W. A. Rogers, "A New Design For Testability Method : Clock Line Control Design," Proc. of the IEEE Custom Integrated Circuits Conference, pp. 26.2.1-26.2.4, May 1993


Domestic Journals

[5] S.-W. Ahn, C.-M. Jung, C.-S. Lim, S.-Y. Lee, and Sanghyeon Baeg, "Clocked Low Power Rail-to-Rail Sense Amplifier for Ternary Content Addressable Memory (TCAM) Application," Journal of the IEEK-SD, vol. 49, no. 2, pp. 39-46, 2012

[4] S.-Y. Lee and Sanghyeon Baeg, "Introduction of Soft Errors in Semiconductor Memories," The Magazine of the ISTK, vol. 2, no. 4, pp. 208-213, 2010

[3] S.-N. Jeong and Sanghyeon Baeg, "Analysis Simultaneously Switching Density Using Ring Oscillator," Journal of the IEEK-SD, vol. 45, no. 9, pp. 79-84, Sep. 2008

[2] J.-K. Oh, M.-S. Kim, and Sanghyeon Baeg, "AC Coupling Capacitor Test using Hysteresis Buffer," The Magazine of the ISTK, vol. 1, no. 2, pp. 130-136, 2008

[1] M.-S. Kim and Sanghyeon Baeg, "Characteristic and Performance of AC-Coupled Channel," The Magazine of the ISTK, vol. 1, no. 3, pp. 189-195, 2008


Domestic Conferences

[23] S.-H. Wi, and Sanghyeon Baeg, "," Korea Test Conference, Jun. 2016

[22] S.-W. No, and Sanghyeon Baeg, "," Korea Test Conference, Jun. 2016

[21] D.-H. Yun, K.-B. Park, G.-Y. Bak, and Sanghyeon Baeg, "Retention Test of DIMM Module by Local Heating," Korea Test Conference, Sep. 2015

[20] M. Waqar, H.-S. Lee, G.-Y. Bak, S. A. Khan, and Sanghyeon Baeg, "DIMM Press-fit Socket Pin Seating Position Effect on Socket to System Board Interconnect," Korea Test Conference, Sep. 2015

[19] H.-S. Lee, and Sanghyeon Baeg, "An Indirect Diagnosis of VTT Power Rail Defect in DDR3 Memory System by Using Intensive Address Switching Test Algorithms," Korea Test Conference, Sep. 2015

[18] C.-S. Lim, G.-Y. Bak, K.-B. Park, and Sanghyeon Baeg, "Retention Time Test on Heavy-Ion-Induced SDRAM Devices," The Institute of Electronics and Information Engineers Conference, Jun. 2015

[17] H-S. Lee, and Sanghyeon Baeg, "A Case Study of JTAG Interface Connection Failure in FPGA System Caused by SMT Defect," Korea Test Conference, Jun. 2014

[16] K.-S. Lee, S.-J. Jeong, K.-B. Park, and Sanghyeon Baeg, "Substitutive Model of the Sense Amplifier Dynamic 2-Cell Incorrect Read Fault of Type 1," Korea Test Conference, Jun. 2013

[15] H.-W. Nam, and Sanghyeon Baeg, "DRAM Word Line Drive Circuit Operation by Hot Carrier Injection," Korea Test Conference, Jun. 2012

[14] S.-J. Jeong, and Sanghyeon Baeg, "March C- using Address Rotation for Detecting Delay Coupling Fault," Korea Test Conference, Jun. 2012 (Best Paper Award)

[13] S.-Y. Lee, H.-W. Nam, and Sanghyeon Baeg, "면적 효율과 고-해상도의 후-보정이 가능한 CMOS 버니어 딜레이 라인 셀 디자인," 한국반도체 학술대회, 2012

[12] I.-G. Kim, and Sanghyeon Baeg, "Implementation of 8051 8-bit Processor with Variable Pipeline Stages," ISOCC Chip Design Contest, Nov. 2010

[11] J.-S. Bae, and Sanghyeon Baeg, "Analysis of VDDmin Shift by Mixed Gate Oxide Breakdown and NBTI in SRAM," Korea Test Conference, Jun. 2010

[10] S.-Y. Lee, S. Z. Kahn, S.-W. Ahn, and Sanghyeon Baeg, "Design of Area Efficient High Resolution CMOS Vernier Delay Line Cell, IEEK Conference 2010

[9] S.-M. Oh, and Sanghyeon Baeg, "Power Saving Model with the Conversion of Parallel Interface to Serial Interface," SoC Conference at Inha University, Mar. 2010

[8] J.-D. Jung, and Sanghyeon Baeg, "Ground Pin Removal Method Implementations for Delay Test in Probe Card Environment," Korea Test Conference, Jun. 2009

[7] J.-K. Oh, M.-S. Kim, and Sanghyeon Baeg, "AC Coupling Capacitor Test using Hysteresis Buffer," Korea Test Conference, Jun. 2008

[6] C.-M. Jung, and Sanghyeon Baeg, "Ground Bounce Effects on the Device under NBTI Stress," Korean Conference on Semiconductors, 2008

[5] T.-W. Choi, and Sanghyeon Baeg, "Ground Bounce Analysis in Impact of NBTI on SRAM Cell," Korea Test Conference, Jun. 2007

[4] J.-S. Bae, and Sanghyeon Baeg, "Analysis of AC Coupling Defect for SRAM Cell,"Korea Test Conference, Jun. 2007

[3] T.-W. Choi, K.-B. Park, J.-S. Bae, S.-N. Jung, and Sanghyeon Baeg, "Ternary CAM IP Design Using 0.18-um CMOS Technology," The Korean Conference on Semiconductors, 2007 (Best Design Award)

[2] K.-B. Park, and Sanghyeon Baeg, "di/dt Analysis Based on Layout Driven Current Path Modeling of CAM Match- line," The Korean Conference on Semiconductors, 2007

[1] J.-S. Bae, and Sanghyeon Baeg, "Analysis and Detection Capacitive Crosstalk Defects Between Memory Cells," Korea Test Conference, Jun. 2006 (Best Paper Award)


Presentation

[4] Sanghyeon Baeg, "Test Correlation at Chip Level & System Level", Nov.20,2014, WRTLT'14(The Fifteenth Workshop on RTL and High Level Testing)

[3] Sanghyeon Baeg, S.-J. Jeong, K.-S. Lee and Xinli Gu, "Metrics Development of Characterizing Test Algorithms Activity in Relation to Physical Memory Structure", March 16-17, 2014, China Semiconductor Technology Internation Conference (CSTIC) 2014

[2] S. Chung, "SiP and Future of Semiconductor Test ", Jun.25,2014, 제 15회 한국테스트학술대회 튜토리얼

[1] Sanghyeon Baeg, "반도체 테스트 동향 및 이슈", Apr.3,2013, 반도체 콜로키움 (반도체 package, test 기술 및 산업 전망)
 

IEEE Standard

54 Members including Sanghyeon Baeg, “1149.6 IEEE Standard for Boundary-Scan Testing of Advanced Digital Network”, IEEE Press, April 2003
 

Books

[3] Interconnect Tests Issues and Strategies, total of 147 pages, Sanghyeon Baeg, 2006, IT-Soc, Korea
[2] CMOS IP Design, total of 73 pages, Sanghyeon Baeg, 2006, IDEC, Korea
[1] UNIX System V Guide Book, total of 655 pages, Sanghyeon Baeg, Kidari Press, 1991, Korea


U.S.A Patents

[12] Chung Sung Soo, Baeg Sang Hyeon, “AC coupled line testing using boundary scan test methodology”, 09/11/2007, USA Patent No. : 7,174,492

[11] S. Baeg, and S. Chung, “Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test”, Aug. 8, 2006, USA Patent Number : 7089463

[10] S. Baeg, S. Chung, and H. Jun, “Programmable test pattern and capture mechanism for boundary scan”, Aug. 8, 2006, USA Patent Number : 7089470

[9] Baeg Sanghyeon , Yu Edward, “Clock generation for testing of integrated circuits”,09/08/1998, USA Patent Number : 5805608

[8] Qureshi Amjad , Baeg Sanghyeon, “Structure and Method for SDRAM dynamic self refresh entry and exit using JTAG”, 08/11/1998, USA Patent Number : 5793776

[7] Baeg Sanghyeon, “Low cost emulation scheme implemented via clock control JTAG controller in a scan environment”, 09/22/1998, USA Patent Number : 5812562

[6] Baeg SangHyeon, Rogers William A., “Integrated circuit having clock-line control and method for testing same”, May 21, 1996, USA Patent Number : 5519713

[5] Qureshi Amjad, Baeg Sanghyeon, “Adaptable scan chains for debugging and manufacturing test purposes”, 08/11/1998, USA Patent Number : 5793776

[4] Kim Heon-cheol, Kim Ho-ryong, Baeg Sang-hyeon, Cho Chang-hyun, “A method of testing single-order address memory”, 01/06/1998, USA Patent Number : 5706293

[3] Baeg Sang-hyeon, Lee Seong-won, “Test circuits and methods for built-in testing integrated devices”, 02/01/2000, USA Patent Number : 6019502

[2] Baeg Sang-hyeon, Kim Heon-cheol, Kim Ho-royng, Cho Chang-hyun, “Serial memory interface using interlaced scan”, 05/19/1998, USA Patent Number : 5754758

[1] Baeg Sanghyeon, Yi Dongsoon, “Self-test circuit and method utilizing interlaced scanning for testing a semiconductor memory device”, June 29, 1999, USA Patent Number : 5917832


PCT Patents

[2] Sanghyeon Baeg, Zahid Ullah, "SRAM BASED ADDRESS GENERATOR FOR EACH LAYER AND ADDRESS GENERATOR INCLUDING THE SAME ", IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY), Publication Number: WO11/071273, Application Number: PCT/KR10/08595 (2010.12.02)

[1] BAEG, Sang-Hyeon, "METHOD OF TESTING SEMICONDUCTOR DEVICE," INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY, Publication Number: WO10/055964, Application Number: PCT/KR08/06757  (2008.11.17)
 

Domestic Patents

[15] 백상현, 알리아메드 "비트 수를 증가시킨 SRAM 기반 TCAM의 동작 방법 및 시스템", 한양대학교 산학협력단출원, 출원번호: 10-2015-0134450, 출원일: 2015.09.23

[14] 백상현, 임철승 "반도체 메모리 장치의 프리차지 제어 회로 및 방법", 한양대학교 산학협력단출원, 출원번호: 10-2015-0073970, 출원일: 2015.05.27

[13] 백상현, 정성수 "리페어 가능한 관통 전극을 갖는 반도체 장치", 한양대학교 산학협력단출원출원번호10-2014-0069928출원일: 2014.06.10 (정보통신산업진흥원(대전사무소))

[12] 백상현, 정현수 "극저온 냉매를 이용한 국부적 저온 챔버", 한양대학교 산학협력단출원출원번호10-2014-0026785출원일: 2014.03.06 ((재)한국연구재단 지원)

[11] 백상현, 이호성 "이중 인라인 메모리 모듈 및 테스트 소켓을 이용한 고속 메모리 콤포넌트 테스트 시스템 및 장치",한양대학교 산학협력단출원출원번호10-2013-0032708출원일: 2013.3.27, 등록번호: 10-141010100000,등록일자: 2014.06.13 (GRRC 7차년도 지원)

[10] 백상현, 남현우 "드라이아이스를 이용한 국부적 저온 챔버 개발",한양대학교 산학협력단출원출원번호10-2012-0149884출원일: 2012.12.20 (GRRC 7차년도 지원)

[9] 백상현울라자히드, "SRAM 기반의 계층별주소 생성장치 그를 포함하는주소 생성장치 (SRAM based address generator for each layer and address generator comprising the same)," 한양대학교산학협력단 출원출원번호10-2009-0121318출원일자: 2009.12.08, 등록번호10-1074495등록일자: 2011.10.11, (지식경제부 ITRC사업실적)

[8] 백상현안상욱배종선신효덕, "레일투레일 저전력전압 센스증폭기", 한양대학교산학협력단 출원,출원번호10-2008-0130513출원일: 2008.12.19, 등록번호10-1061634등록일: 2011 826 (지식경제부ITRC사업 지원)

[7] 백상현, "이벤트시간 측정방법 회로", 한양대학교산학협력단 출원출원번호10-2010-0049204출원일: 2010.05.26, 등록번호10-1061634  등록일: 2011.07.25, (GRRC 6차년도 지원실적(등록))

[6] 백상현, "반도체소자의 테스트방법(파워/그라운드 제거테스트 방법)", 한양대학교 산학협력단출원출원번호2008-0113772출원일: 2008.11.17, 등록번호10-1002102등록일: 201012 10(GRRC 5차년도실적(등록))

[5] 백상현배종선, "반도체 메모리장치 그것의 테스트방법," 한국전자통신연구원한양대학교 산학협력단공동출원출원번호2007-0083963출원일: 2007.08.21, 등록번호10-0919819등록일: 2009.09.24 (IT-SoC 설계실습프로젝트실적(출원))

[4] 백상현배종선, "단위셀 간의연결고장 테스트를위한 반도체메모리 장치 테스트방법"(SEMICONDUCTOR MEMORY DEVICE FOR TESTING CAPACITIVE CROSSTALK DEFECTS BETWEEN UNIT CELLS AND TEST METHOD THEREIN);, 한국전자통신연구원한양대학교 산학협력단출원번호2007-0071751출원일: 2007.07.18, 등록번호10-0919819-0000등록일: 2009.02.19

[3] 백상현, "메모리폴트 시뮬레이션응용에서 시간고려고장 모델 물리적구조 기술", 한양대학교 산학협력단출원출원번호10-2011-0021822출원일: 2011.03.11

[2] 백상현박성주사이드모흐신, "내용주소화 메모리의다중 고장을 허용하기위한 방법 장치", 한양대학교 산학협력단출원출원번호10-2010-0120903출원일: 2010.11.30

[1] 백상현, "반도체소자의 테스트방법 이를 위한노이즈 발생방법(di/dt)", 한양대학교 산학협력단출원출원번호10-2010-0045553출원일: 2010.05.14 (GRRC 실적)


Software License

[1] 백상현이순영, "메모리 비트 뷰어", 한양대학교 산학협력단, 2009/11/25, 등록번호 2009-01-121-006532