작성일 : 12-07-12 11:16
Publication
 글쓴이 : webmaster
조회 : 6,863  
In Progressing

- Under preparation
   S. Lee et al., "Modeling SRAM stability of Resultant Current Pulse by High-Energy Ion" 

- Submitted Papers 
   S. Lee et al., "Memory Reliability Analysis for Multiple Block Effect of Soft Errors," under review
   S. M. Abbas et al., "An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory," under review


International Journals
 
18) Zahid Ullah and Sanghyeon Baeg, "Vertically Partitioned SRAM-based Ternary Content Addressable Memory," accepted for publication in International Journal of Engineering and Technology, 2012
 
17) Sanghyeon Baeg, Soonyoung Lee, Geun Yong Bak, Hyunsoo Jeong, and Sang Hoon Jeon, "Comparative Study of MC-50 and ANITA Neutron Beams by Using 55 nm SRAM," Journal of the Korean Physical Society, vol. 61, no. 5, pp. 749-753, 2012 

16) Zahid Ullah, Ilgon Kim, Sanghyeon Baeg, “Hybrid Partitioned SRAM-based Ternary Content Addressable Memory”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, Dec. 2012

15) Jongsun Bae, Sanghyeon Baeg, Sungju Park, "Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress," accepted for publication in IEEE Trans. Instrum. Meas., 2012

14) Soonyoung Lee, Sanghyeon Baeg, and Pedro Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors," IEEE Trans. Nucl. Sci., Vol. 58, No. 5, pp.2483-2492, Oct. 2011,(supported by GRRC) [Paper Link]

13) Juan Antonio Maestro, Pedro Reviriego, Sang H. Baeg, Shi-Jie Wen, and Richard Wong, "Mitigating the effects of large Multiple Cell Upsets (MCUs) in memories," ACM Transactions on Design Automation of Electronic Systems, Volume 16, Issue 4, pp. 45:1-45:10, October 2011 [Paper Link]

12) Pedro Reviriego Vasallo, Juan Antonio Maestro De la Cuerda, Sang H. Baeg, Shi-Jie Wen, Richard Wong, "Protection of Memories Suffering MCUs through the Selection of the Optimal Interleaving Distance," IEEE Trans. Nucl. Sci., Vol. 57, No. 4, pp. 2124-2128, Aug. 2010 [Paper Link]

11) Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg, "Optimizing Scrubbing Sequences for Advanced Computer Memories," IEEE Trans. Device Mater. Rel., Vol. 10, No. 2, pp. 192-200, June. 2010 [Paper Link]

10) Sanghyeon Baeg, ShiJie Wen, Richard Wong, "Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals," IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 57, No. 4, pp. 814-822, April 2010 (supported by ITRC,GRRC) [Paper Link]

9) Sanghyeon Baeg, ShiJie Wen, Richard Wong, "SRAM Interleaving Distance Selection with a Soft Error Failure Model," IEEE Trans. Nucl. Sci., Vol. 56, No. 4, pp. 2111-2118, Aug. 2009 (supported by ITRC) [Paper Link]

8) S. Baeg, "Null Detector Circuit Design Scheme for Detecting Defective AC Coupled Capacitors in Differential Signaling," IEEE Trans. Instrum. Meas., Vol. 58, No. 8, pp.2544-2556, Aug. 2009 (supported by GRRC,ITRC) [Paper Link]

7) S. Baeg, "A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins," IEEE Trans. Instrum. Meas., Vol. 58, No. 10, pp. 3450-3456, Oct. 2009 (supported by ITRC,GRRC) [Paper Link]

6) S. Baeg, "Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line," IEEE Trans. Circuits Syst. I, Reg. Papers, Vol.55, No.6, pp. 1485-1494, July 2008 (supported by GRRC) [Paper Link]

5) Sanghyeon Baeg, "Low Power Configuration Strategy of TCAM Lookup Table," IEICE Trans. on Communications, Vol. 91-B, NO.3, pp 915-917, March 2008 (supported by GRRC) [Paper Link]

4) Sanghyeon Baeg, “Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks,” IEEE Trans. Comput-Aided Design Integr. Circuits Syst., Vol. 26, No. 12, pp. 2215-2221, Dec. 2007 (supported by Hanyang University) [Paper Link]

3) P. Min, H. Yi, J. Song, S. Baeg, and S. Park, “Efficient Interconnect Test Patterns for Crosstalk and Static Faults,” IEEE Trans. Comput-Aided Design Integr. Circuits Syst., Vol. 25, No. 11, pp. 2605-2608, Nov. 2006 (supported by System IC 2010 and BK 21) [Paper Link]

2) S. Baeg and S. Chung, “Analytical Test Buffer Design For Differential Signaling I/O Buffers By Error Syndrome Analysis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 13, No. 3, pp. 370-383, March 2005 [Paper Link]

1) Sanghyeon Baeg, William A. Rogers, "A Cost-Effective Design for Testability: Clock Line Control and Test Generation Using Selective Clocking," IEEE Trans. Comput-Aided Design Integr. Circuits Syst., Vol. 18, No. 6, pp. 850-861, Jun 1999 [Paper Link]



Domestic Journals

5) Sangwook Ahn, Changmin Jung, Chulseung Lim, Soonyoung Lee, and Sanghyeon Baeg, "Clocked Low Power Rail-to-Rail Sense Amplifier for Ternary Content Addressable Memory (TCAM) Application," 대한 전자공학회논문지, SD 편 제 49권 제 2호, pp.39-46, 2012, (supported by GRRC)

4) Soonyoung Lee, Sanghyeon Baeg, "Introduction of Soft Errors in Semiconductor Memories", The Magazine of the ISTK, Vol. 2, No. 4, pp.208-213, 2010, ISSN:2004-0208 (supported by GRRC)
(이순영, 백상현, "반도체 메모리에서 발생하는 소프트에러에 대한 소개", 반도체 테스트 학회지, 제2권, 제4호, pp.208-213, 2010, ISSN:2005-0208 (supported by GRRC)

3) Sang-Nam Jeong and Sanghyeon Baeg, "Analysis Simultaneously Switching Density Using Ring Oscillator", Journal of IEEK-SD, Vol. 45, No. 9, pp. 79-84, SEPTEMBER 2008, ISSN:1229-6368, (supported by GRRC)
(정상남, 백상현, "Ring Oscillator를 이용한 신호의 동시 스위칭 밀도 분석", 대한전자공학회 논문지, SD편, 제 45권, 제 9호, pp. 79-84, 2008년)

2) J. Oh, M. Kim, S. Baeg, “AC Coupling Capacitor Test using Hysteresis Buffer”, The Magazine of the ISTK, Vol. 1, No. 2, 2008, pp. 130-136, ISSN : 2005-0208

1) M. Kim, S. Baeg, “Characteristic and Performance of AC-Coupled Channel”, The Magazine of the ISTK, Vol. 1, No. 3, 2008, pp. 189-195, ISSN : 2005-0208



International Conferences
 
24) Sanghyeon Baeg, Soonyoung Lee, Ken Yong Park, ShiJie Wen, and Richard Wong, "High-Energy Alpha Particle SEU Measurements for Flip Chip Devices," IEEE Santa Clara Valley CPMT Society Chapter Workshop, Oct. 25, 2012
 
23) Sanghyeon Baeg, Jongsun Bae, Soonyoung Lee, Chul Seung Lim, Sang Hoon Jeon, and Hyeonwoo Nam, "Soft Error Issues with Scaling Technologies," The 21st Asian Test Symposium (ATS'12), Toki Messe Niigata Convetion Center, Niigata, Japan, Nov. 19-22, 2012
 
22) J.A. Maestro, A. Sánchez-Macián, P. Reviriego, S. Baeg, “Optimizing the Protection of Narrow Values in Memories Protected with Hamming Codes,” Proc. of the RADECS Conf., Biarritz (France), Sep. 2012.
 
21) Sanghyeon Baeg, Pierre Chia, ShiJie Wen, and Richard Wong, "DRAM Failure Cases Under Hot-Carrier Injection," Physical and Failure Analysis of Integrated Circuits (IPFA), July 2011, pp. 1-3 (supported by GRRC) [Paper Link]

20) Reviriego, P., Maestro, J.A., and Sanghyeon Baeg, "Designing Ad-Hoc Scrubbing Sequences to Improve Memory Reliability against Soft Errors," Design Automation Conference (DAC), June 2011, pp. 700-705 (supported by GRRC) [Paper Link]

19) Sanghyeon Baeg, Hyeonwoo Nam, ShiJie Wen and Richard Wong, "AC-DC Factor Sensitivity for DRAM Components Lifetime under Hot-Carrier Injection," Reliability Physics Symposium (IRPS), April 2011, pp. 2D.1.1-1.4 (supported by GRRC) [Paper Link]

18) Syed Mohsin Abbas, Sanghyeon Baeg and Sungju Park, "Multiple Cell Upsets Tolerant Content-Addressable Memory," Reliability Physics Symposium (IRPS), April 2011, pp. SE.1.1-1.5 (supported by GRRC) [Paper Link]

17) Changmin Jung, Sanghyeon Baeg, ShiJie Wen, and Richard Wong, "Design Method of NOR-Type Comparison Circuit in CAM with Ground Bounce Noise Considerations," International Symposium on Quality Electronic Design (ISQED), March 2011 (supported by GRRC)[Paper Link]

16) C.-F. Chia, S.-J. Wen, S.H. Baeg, "New DRAM HCI Qualification Method Emphasizing on Repeated Memory Access", IEEE International Integrated Reliability Workshop (IIRW), Oct. 2010 [Paper Link]

15) Zahid Ullah, Sanghyeon Baeg, "Vertically Partitioned SRAM-based Ternary Content Addressable Memory," IEEE International Conference on Intelligence and Information Technology(ICIIT 2010), Oct. 2010 (supported by GRRC)

14) Jongsun Bae, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, "SRAM Cell Reliability Degradations due to Cell Crosstalk," IEEE International Integrated Reliability Workshop (IIRW), Oct. 2010 (supported by GRRC) [Paper Link]

13) Soonyoung Lee, Sanghyeon Baeg, and Pedro Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors", IEEE International Integrated Reliability Workshop (IIRW), Oct. 2010 (supported by GRRC) [Paper Link]

12) Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg, Shijie Wen and Richard Wong, "Selection of the Optimal Interleaving Distance for Memories Suffering MCUs", 10th European Conference on Radiation Effects on Components and Systems, sep. 2009 [Paper Link]

11) Sanghyeon Baeg, Pedro Reviriego, Juan Antonio Maestro, ShiJie Wen, Richard Wong, "Analysis of a Multiple Cell Upset Failure Model for Memories", SELSE 5 Workshop - Silicon Errors in Logic - System Effects, March 24th, 2009 in Stanford University, (supported by ITRC)[Paper Link]

10) Hyo-deok Shin, Sang-wook Ahn, Tae-hoon Song, Sang-hyeon Baeg, "Analysis of Low Power Sensor Node Using Data Compression", 8th IFAC International Conference on FeT'2009, May 20-22, 2009, pp34-39(supported by GRRC) [Paper Link]

9) Sanghyeon Baeg, ShiJie Wen, Richard Wong, "SRAM Interleaving Distance Selection with a Soft Error Failure Model", RADECS 2008 Workshop (supported by ITRC)

8) Luis Boluna*, Kelvin Qiu*, Ehsan Kabir*, Susmita Mutsuddy*, Daniel Ho*, and Dr. Sang Baeg**, *Cisco Systems and ** University of Hanyang (South Korea) "Advances in 7.5Gb/s SerDes Modeling using IBISv4.2(VHDL-AMS and Verilog-AMS)" IBIS Summit Meeting Feb 7, 2008 Santa Clara, CA U.S.A [Paper Link]

7) H. Jun, S. Chung, and S. Baeg, “Removing JTAG Bottleneck in System Interconnect Test”, Proc. Int’l Test Conf., IEEE Press, 2004[Paper Link]

6) S. Chung and S. Baeg “AC-JTAG: Empowering JTAG beyond Testing DC Nets,” Proc. Int’l Test Conf., IEEE Press, 2001, pp 30-37 [Paper Link]

5) Embedded Memory BIST of Serial Test Vector Generation, Serial Output Comparison, Sanghyeon Baeg, H.R. Kim, C.H. Cho, H.C. Kim, Second International Test Synthesis Workshop, May 8-10, 1995

4) Hybrid Design For Testability Combining Scan and Clock Line Control and Method For Test Generation, Sanghyeon Baeg, William A. Rogers, International Test Conference, Oct. 1994 [Paper Link]

3) A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits, Sanghyeon Baeg, William A. Rogers, International Conference on Computer Design, Oct. 1994 [Paper Link]

2) Enhancing Temporal Testability and Its Effects on Design and Test Generation, Sanghyeon Baeg, William A. Rogers, Presented in International Workshop on The Economics of Design, Test and Manufacturing, May 1994 [Paper Link]

1) A New Design For Testability Method : Clock Line Control Design, Sanghyeon Baeg, William A. Rogers in Custom Integrated Circuits Conference, May, 1993 [Paper Link]



Domestic Conferences

15) Hyeonwoo Nam , Sanghyeon Baeg,  " DRAM Word Line Driver Circuit Operation by Hot Carrier Injection ", 2012 Korea Test Conference, June 2012
(남현우, 백상현, "Hot Carrier Injection에 의한 DRAM Word Line Driver 회로 동작의 변화", 제 13회 한국테스트학술대회, June 2012) supported by GRRC and IPC

14) SeungJae Jeong , Sanghyeon Baeg,  "March C- using address rotation for detecting Delay Coupling Fault", 2012 Korea Test Conference, June 2012
(정승재, 백상현, " Delay Coupling Fault 감지를 위한 March C-의 address rotation", 제 13회 한국테스트학술대회(최우수논문상), June 2012) supported by Huawei

13) 이순영, 남현우, 백상현, "면적 효율과 고-해상도의 후-보정이 가능한 CMOS 버니어 딜레이 라인 셀 디자인", "제19회 한국반도체학술대회, 2012" supported by GRRC and IDEC

12) Ilgon Kim, Sanghyeon Baeg, " Implementation of 8051 8-bit Processor with Variable Pipeline Stages", 2010 ISOCC Chip Design Contest, November 2010
(김일곤, 백상현, "가변 파이프라인 스테이지를 적용한 8051 8-bit 프로세서의 설계", 2010 ISOCC Chip Design Contest, 2010년 11월 22일)

11) Jongsun Bae, Sanghyeon Baeg, "Analysis of VDDmin Shift by Mixed Gate Oxide Breakdown and NBTI in SRAM," The 11th Korean Test Conference, June 2010
(배종선, 백상현, "복합적인 고장에 의한 VDDmin Shift의 관계 분석," 제11회 한국테스트학술대회, 2010년 6월 29일) supported by GRRC

10) Soonyoung Lee, Sikandar Z. Khan, Sangwook Ahn, Sanghyeon Baeg, "Design of Area Efficient High Resolution CMOS Vernier Delay Line Cell", ieek Conference, 2010
(이순영, Sikandar Z. Khan, 안상욱, 백상현, "면적 효율과 고-분해능을 가지는 CMOS 버니어 딜레이 라인 셀 디자인", 대한전자공학회 하계종합학술대회, 2010) supported by GRRC

9) "Power Saving Model with the Conversion of Parallel Interface to Serial Interface", SoC Conference at Inha University, May., 2010
(오성민, 백상현, "병렬인터페이스와 직렬이터페이스 변환의 전력소모 모델, "2010 SoC 학술대회, 2010년 5월 1일) supported by ETRI

8) Jae Doo Jung, Sanghyeon Baeg, "Ground Pin Removal Method Implementations for Delay Test in Probe Card Environment", The 10th Korea Test Conference, 2009, (supported by GRRC)
(정재두, 백상현, "그라운드 핀의 제거 방법을 통한 지연 테스트의실현을 위한 프로브카드에서의 그라운드 핀 제거방법 구현", 제 10회 한국테스트학술대회, 2009) 

7) JungKyun Oh, Minsuk Kim, Sanghyeon Baeg, "AC Coupling Capacitor Test using Hysteresis Buffer", The 9th Korea Test Conference, 2008, ISSN:2005-0208, (supported by GRRC)
(오정균, 김민석, 백상현, “Hysteresis 버퍼를 이용한 AC커플링 커패시터 테스트” 제 9회 한국테스트학술대회, 2008)

6) Changmin Jung, Sanghyeon Baeg, "Ground bounce effects on the Devices under NBTI stress,", The 15th Korean Conference on Semiconductors, 2008 (suppored by GRRC)
(정창민, 백상현, "Ground bounce effects on the Devices under NBTI stress," 제15회 한국반도체학술대회, 2008)

5) Taewon Choi, Sanghyeon Baeg, "Ground Bounce Analysis in Impact of NBTI on SRAM Cell," The 8th Korea Test Conference, 2007, (supported by GRRC,IT-SoC)
(최태원, 백상현, "NBTI가 발생한 SRAM Cell의 Ground Bounce 영향 분석," 제 8회 한국 테스트 학술대회, 2007)

4) Jongsun Bae, Sanghyeon Baeg, "Analysis of AC Coupling Defect for SRAM Cell", The 8th Korea Test Conference, 2007 (supported by IT-Soc, GRRC)
(배종선, 백상현, "SRAM 셀 간의 AC 커플링 고장의 해석," 제 8회 한국 테스트 학술대회, 2007)

3) Taewon Choi, KyoungBae Park, Jongsun Bae, Sangnam Jung, Sanghyeon Baeg, “Ternary CAM IP Design Using 0.18-um CMOS Technology”, The Korean Conference on Semiconductors, 2007 (Best Design Award)

2) KyoungBae Park, Sanghyeon Baeg, “di/dt Analysis Based on Layout Driven Current Path Modeling of CAM Match- line”, The Korean Conference on Semiconductors, 2007

1) Jongsun Bae, Sanghyeon Baeg, “Analysis and Detection Capacitive Crosstalk Defects Between Memory Cells”, The 7th Korea Test Conference, June, 2006, pp. 157-162 (Best Paper award, supported by IT-SoC)
(배종선, 백상현, “메모리 셀간의 Crosstalk 고장 분석 및 테스트 방법”, 제 7회 한국 테스트학술대회, June, 2006, pp. 157-162 (우수논문상))



Book

3) Interconnect Tests Issues and Strategies, total of 147 pages, 백상현, 2006, IT-Soc, Korea

2) CMOS IP Design, total of 73 pages, 백상현, 2006, IDEC, Korea

1) UNIX System V Guide Book, total of 655 pages, Compiled by Sanghyeon Baeg, Kidari Press, 1991, Korea



IEEE Standard

1) 54 Members including S. Baeg, “1149.6 IEEE Standard for Boundary-Scan Testing of Advanced Digital Network”, IEEE Press, April 2003[Link]



U.S.A Patents

12) Chung Sung Soo, Baeg Sang Hyeon, “AC coupled line testing using boundary scan test methodology”, 09/11/2007, USA Patent Number : 7,174,492

11) S. Baeg, and S. Chung, “Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test”, Aug. 8, 2006, USA Patent Number : 7089463

10) S. Baeg, S. Chung, and H. Jun, “Programmable test pattern and capture mechanism for boundary scan”, Aug. 8, 2006, USA Patent Number : 7089470

9) Baeg Sanghyeon , Yu Edward, “Clock generation for testing of integrated circuits”,09/08/1998, USA Patent Number : 5805608 

8) Qureshi Amjad , Baeg Sanghyeon, “Structure and Method for SDRAM dynamic self refresh entry and exit using JTAG”, 08/11/1998, USA Patent Number : 5793776

7) Baeg Sanghyeon, “Low cost emulation scheme implemented via clock control JTAG controller in a scan environment”, 09/22/1998, USA Patent Number : 5812562

6) Baeg SangHyeon, Rogers William A., “Integrated circuit having clock-line control and method for testing same”, May 21, 1996, USA Patent Number : 5519713

5) Qureshi Amjad, Baeg Sanghyeon, “Adaptable scan chains for debugging and manufacturing test purposes”, 08/11/1998, USA Patent Number : 5793776

4) Kim Heon-cheol, Kim Ho-ryong, Baeg Sang-hyeon, Cho Chang-hyun, “A method of testing single-order address memory”, 01/06/1998, USA Patent Number : 5706293

3) Baeg Sang-hyeon, Lee Seong-won, “Test circuits and methods for built-in testing integrated devices”, 02/01/2000, USA Patent Number : 6019502

2) Baeg Sang-hyeon, Kim Heon-cheol, Kim Ho-royng, Cho Chang-hyun, “Serial memory interface using interlaced scan”, 05/19/1998, USA Patent Number : 5754758

1) Baeg Sanghyeon, Yi Dongsoon, “Self-test circuit and method utilizing interlaced scanning for testing a semiconductor memory device”, June 29, 1999, USA Patent Number : 5917832


PCT Patents

2) Sanghyeon Baeg, Zahid Ullah, "SRAM BASED ADDRESS GENERATOR FOR EACH LAYER AND ADDRESS GENERATOR INCLUDING THE SAME ", IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY), Publication Number: WO11/071273, Application Number: PCT/KR10/08595  (2010.12.02)

1) BAEG, Sang-Hyeon, "METHOD OF TESTING SEMICONDUCTOR DEVICE," INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY, Publication Number: WO10/055964, Application Number: PCT/KR08/06757  (2008.11.17)  


국내 특허 (등록) 

6) 백상현, 울라자히드, "SRAM 기반의 계층별 주소 생성 장치 및 그를 포함하는 주소 생성 장치 (SRAM based address generator for each layer and address generator comprising the same)," 한양대학교 산학협력단 출원, 출원번호: 10-2009-0121318, 출원일자: 2009.12.08, 등록번호: 10-1074495, 등록일자: 2011.10.11, (지식경제부 ITRC사업 실적)

5) 백상현, 안상욱, 배종선, 신효덕, "레일투레일 저전력 전압 센스 증폭기", 한양대학교 산학협력단 출원,출원번호: 10-2008-0130513, 출원일: 2008.12.19, 등록번호: 10-1061634, 등록일: 2011년 8월 26일 (지식경제부 ITRC사업 지원)

4) 백상현, "이벤트 시간 측정 방법 및 회로", 한양대학교 산학협력단 출원, 출원번호: 10-2010-0049204, 출원일: 2010.05.26, 등록번호: 10-1061634  등록일: 2011.07.25, (GRRC 6차년도 지원실적(등록))

3) 백상현, "반도체 소자의 테스트 방법(파워/그라운드 핀 제거 테스트 방법)", 한양대학교 산학협력단 출원, 출원번호: 2008-0113772, 출원일: 2008.11.17, 등록번호: 10-1002102, 등록일: 2010년 12월 10일 (GRRC 5차년도 실적(등록))

2) 백상현, 배종선, "반도체 메모리 장치 및 그것의 테스트 방법," 한국전자통신연구원, 한양대학교 산학협력단 공동출원, 출원번호: 2007-0083963, 출원일: 2007.08.21, 등록번호: 10-0919819, 등록일: 2009.09.24 (IT-SoC 설계실습프로젝트 실적(출원))

1) 백상현, 배종선, "단위셀 간의 연결고장 테스트를 위한 반도체 메모리 장치 및 테스트 방법"(SEMICONDUCTOR MEMORY DEVICE FOR TESTING CAPACITIVE CROSSTALK DEFECTS BETWEEN UNIT CELLS AND TEST METHOD THEREIN);, 한국전자통신연구원, 한양대학교 산학협력단, 출원번호: 2007-0071751, 출원일: 2007.07.18, 등록번호: 10-0919819-0000, 등록일: 2009.02.19 


국내 특허 (출원) 

3) 백상현, "메모리 폴트 시뮬레이션 응용에서 시간고려 고장 모델 및 물리적 구조 기술", 한양대학교 산학협력단 출원, 출원번호: 10-2011-0021822, 출원일: 2011.03.11 

2) 백상현, 박성주, 사이드모흐신, "내용 주소화 메모리의 다중 셀 고장을 허용하기 위한 방법 및 장치", 한양대학교 산학협력단 출원, 출원번호: 10-2010-0120903, 출원일: 2010.11.30 

1) 백상현, "반도체 소자의 테스트 방법 및 이를 위한 노이즈 발생방법(di/dt)", 한양대학교 산학협력단 출원, 출원번호: 10-2010-0045553, 출원일: 2010.05.14 (GRRC 실적)



프로그램 등록

1) 백상현, 이순영, "메모리 비트 맵 뷰어", 한양대학교 산학협력단, 2009/11/25, 등록번호 2009-01-121-006532 



졸업 논문

14) Sung Min Oh, "A Reliability Study of 40G Ethernet Testing Instrument", Master's degree thesis in Hanyang Univ, August 2011
(오성민, "40G 이더넷 계측기의 신뢰성 연구", 석사학위 논문, 2011년 8월)

13) Il Gon Kim, "R8051 implementation and power consumption analysis", Master's degree thesis in Hanyang Univ, August 2011
(김일곤, "R8051 구현 및 전력소모 분석", 석사학위 논문, 2011년 8월)

12) Jae Doo Jung, "High speed design for the performance between the difference of channel and number of ground-via of the 40G/100G ethernet", Master's degree thesis in Hanyang Univ, August 2010
(정재두, "40G/100G ethernet 고속보드 설계 시 채널특성 및 그라운드 비아에 따른 성능분석", 석사학위 논문, 2011년 2월)

11) Sikandar Muhammad Zulqarnain Khan, "High resolution distance measurement laser range finder system", Master's degree thesis in Hanyang Univ, August 2010
(Sikandar Muhammad Zulqarnain Khan, "고-분해능 거리측정 LRF 시스템", 석사학위 논문, 2010년 8월)

10) Zahid Ullah, "SRAM-based Ternary Content Addressable Memory", Master's degree thesis in Hanyang Univ, February 2010
(Zahid Ullah, "SRAM 기반의 TCAM 설계", 석사학위 논문, 2010년 2월)

9) Sangwook Ahn, "The Design of Pipelined High-speed 8-bit Microcontroller and Memory Expansion", Master's degree thesis in Hanyang Univ, February 2010
(안상욱, "파이프라인 고속 8비트 마이크로콘트롤러 및 메모리 확장 설계", 석사학위 논문, 2010년 2월)

8) Hyodeok Shin, "Implementation of High Speed 8-bit Microprocessor with Variable Pipeline Stages", Master's degree thesis in Hanyang Univ, August 2009
(신효덕, "가변 스테이지 파이프라인을 적용한 고속 8비트 마이크로프로세서의 설계", 석사학위 논문, 2009년 8월)

7) Changmin Jung, "NOR CAM Compare Cell Size Determination with the Groung Bounce Noise Consideration", Master's degree thesis in Hanyang Univ, February 2009
(정창민, "NOR CAM 매치라인에 미치는 그라운드 바운스 노이즈 분석과 그것을 고려한 비교 셀의 크기 결정법에 대한 연구", 석사학위 논문, 2009년 2월)

6) Minsuk Kim, "High-speed Channel Characteristic and Performance Measurement Methodologies", Master's degree thesis in Hanyang Univ, February 2009
(김민석, "고속 통신 채널의 특성 및 성능 측정 방법에 관한 연구", 석사학위 논문, 2009년 2월)

5) JungKyun Oh, "AC Coupling Capacitor Test using Hysteresis Buffer", Master's degree thesis in Hanyang Univ, August 2008
(오정균, "Hysteresis 버퍼를 이용한 AC 커플링 커패시터 테스트", 석사학위 논문, 2008년 8월)

4) Sangnam Jung, "Ground Bounce Noise Analysis and Signal Delay Caused by Signal Switching of Other Part of Circuit", Master's degree thesis in Hanyang Univ, February 2008
(정상남, "그라운드 바운스 노이즈 분석 및 주변 회로의 스위칭에 다른 신호 지연 분석", 석사학위 논문, 2008년 2월)

3) Jongsun Bae, "Diagnosis and Test Method of Capacitive Crosstalk Defects between Memory Cells Using Bit-Line Negative Voltage Stress", Master's degree thesis in Hanyang Univ, August 2007
(배종선, "비트라인 네거티브 전압 스트레스를 이용한 메모리 셀 간의 Crosstalk 고장의 진단 및 테스트 방법", 석사학위 논문, 2007년 8월)

2) Taewon Choi, "TCAM Design and Performance Analysis of TCAM Cell Under NBTI Impact", Master's degree thesis in Hanyang Univ, August 2007
(최태원, "TCAM 구현 및 TCAM 셀의 NBTI하의 성능분석", 석사학위 논문, 2007년 8월)

1) Kyoungbae Park, "Di/dt Analysis and Ground Bounce Reduction Scheme in Content Addressable Memory", Master's degree thesis in Hanyang Univ, August 2007
(박경배, "CAM의 di/dt 분석 및 주파수특성 분석을 통한 그라운드바운스의 감소방안", 석사학위 논문, 2007년 8월)